87 lines
3.6 KiB
C
87 lines
3.6 KiB
C
/**
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* The page direcotry and the page table have very specific
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* entry formats.
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*
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* They will be defined here, and constants will be properly allocated.
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*/
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/**
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* Page directory
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* containes 1024 4 byte entries, making them 4KiB each.
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*
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* In the page directory, each entry points to a page table.
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*
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*
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* Page Directory Entry
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*
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* (this is following the page size of 0, or 4KiB)
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* bits:
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* 31 - 12 : Bits 31-12 of address
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* 11 - 8 : AVL
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* 7 : PS
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* 6 : AVL
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* 5 : A
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* 4 : PCD
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* 3 : PWT
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* 2 : U/S
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* 1 : R/W
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* 0 : P
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*
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*
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* The address field represnets the physical address of the page table that manages the four megabytes at that point.
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* It is very important that this address by 4KiB aligned. As the remainder of bytes are overwritten by access bits and such.
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*
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* P: Present
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* If the bit is set, the page is actually in physical memory at the moment. For example, when a page is swapped out, it is not in physical memory and therefor not 'Present'.
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* If a page is called, but not present, a page fault will occur, and the OS should handle it.
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* R/W: Read/Write
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* If the big is set, the page is read/write. Otherwise, it is read-only. The WP bit in CR0 determines if this is only applied to userland, always giving the kernel write access (the default)
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* or both userland and the kernel. (see Intel Manuals 3A 2-20)
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* U/S: User/Supervisor
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* Controls access to the page based on privelege level. If the bit is set, then the page may be accessed by all; if the bit is not set, however,
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* only the supervisor can access it. For ap age directory entry, the user bit controls access to all the pages referenced by the page directory entry.
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* Therefore if you wish to make a page a user page, you must set the bit in the releveant page directory, as well as the page table entry.
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* PWT: Write-through
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* Controls Write-through abilities of the page. If the bit is set, write-through caching is enabled.
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* If not, then write-back is enabled instead.
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* PCD: Cache Disable
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* Cache disable bit, if the bit is set, the page will not be cached. Otherwise, it will be.
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* A: Accessed
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* Accessed is used to discover whether a PDE or PTE was read during virtual address translation. If it has, then the bit is set, otherwise it is not.
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* Note that, this bit will not be cleared by the CPU, so that burden falls on the OS (if its needed at all).
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* D: Dirty
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* Dirty is used to determine wether a page has been written to.
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* PS: Page Size (always 0, since we're using 4KiB pages)
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* Stores the page size for that specific entry. If the bit is set, then the PDE maps a page that is 4MiB in size. Otherwise, it maps to a 4KiB page table.
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* AVL: Available
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* These bits are unused and are free for the OS to use for accounting information.
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*/
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/**
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* Page Table
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*
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* In each page table, as it is, there are also 1024 entries. Each entry points to a 4KiB physical page frame.
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*
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* These are called page table entries, and are very similar to the entries described above.
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*
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* The first item is a 4KiB aligned physical address. However, these point to a 4KiB block of physical memory, which si then mapped to that location in the page table and driectory.
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*
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* 31 - 12 : Bits 31-12 of address
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* 11 - 9 : AVL
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* 8 : G
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* 7 : PAT
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* 6 : D
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* 5 : A
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* 4 : PCD
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* 3 : PWT
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* 2 : U/S
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* 1 : R/W
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* 0 : P
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*
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* G: Global
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* Tells the processor not to invalidate the TLB entry corresponding to the page upon a MOV to CR3 instruction.
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* Bit 7 (PGE) in CR4 must be set to enable global pages.
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* PAT: Page Attribute Table
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* If PAT is supported, then PAT along with PCD and PWT shall indicate the memory caching type. Otherwise, it is reserved and must be set to 0.
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*/
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