/**
 * The page direcotry and the page table have very specific
 * entry formats.
 *
 * They will be defined here, and constants will be properly allocated.
 */

/**
 * Page directory
 * containes 1024 4 byte entries, making them 4KiB each.
 *
 * In the page directory, each entry points to a page table.
 *
 *
 * Page Directory Entry
 *
 * (this is following the page size of 0, or 4KiB)
 * bits:
 * 31 - 12	: Bits 31-12 of address
 * 11 - 8 	: AVL
 * 7 		: PS
 * 6		: AVL
 * 5		: A
 * 4		: PCD
 * 3 		: PWT
 * 2 		: U/S
 * 1		: R/W
 * 0		: P
 *
 *
 * The address field represnets the physical address of the page table that manages the four megabytes at that point.
 * It is very important that this address by 4KiB aligned. As the remainder of bytes are overwritten by access bits and such.
 *
 * P: Present
 * 	If the bit is set, the page is actually in physical memory at the moment. For example, when a page is swapped out, it is not in physical memory and therefor not 'Present'.
 * 	If a page is called, but not present, a page fault will occur, and the OS should handle it.
 * R/W: Read/Write
 * 	If the big is set, the page is read/write. Otherwise, it is read-only. The WP bit in CR0 determines if this is only applied to userland, always giving the kernel write access (the default)
 * 	or both userland and the kernel. (see Intel Manuals 3A 2-20)
 * U/S: User/Supervisor
 * 	Controls access to the page based on privelege level. If the bit is set, then the page may be accessed by all; if the bit is not set, however,
 * 	only the supervisor can access it. For ap age directory entry, the user bit controls access to all the pages referenced by the page directory entry.
 * 	Therefore if you wish to make a page a user page, you must set the bit in the releveant page directory, as well as the page table entry.
 * PWT: Write-through
 * 	Controls Write-through abilities of the page. If the bit is set, write-through caching is enabled.
 * 	If not, then write-back is enabled instead.
 * PCD: Cache Disable
 * 	Cache disable bit, if the bit is set, the page will not be cached. Otherwise, it will be.
 * A: Accessed
 * 	Accessed is used to discover whether a PDE or PTE was read during virtual address translation. If it has, then the bit is set, otherwise it is not.
 * 	Note that, this bit will not be cleared by the CPU, so that burden falls on the OS (if its needed at all).
 * D: Dirty
 * 	Dirty is used to determine wether a page has been written to.
 * PS: Page Size (always 0, since we're using 4KiB pages)
 * 	Stores the page size for that specific entry. If the bit is set, then the PDE maps a page that is 4MiB in size. Otherwise, it maps to a 4KiB page table.
 * AVL: Available
 * 	These bits are unused and are free for the OS to use for accounting information.
 */

/**
 * Page Table
 *
 * In each page table, as it is, there are also 1024 entries. Each entry points to a 4KiB physical page frame.
 *
 * These are called page table entries, and are very similar to the entries described above.
 *
 * The first item is a 4KiB aligned physical address. However, these point to a 4KiB block of physical memory, which si then mapped to that location in the page table and driectory.
 *
 * 31 - 12	: Bits 31-12 of address
 * 11 - 9 	: AVL
 * 8 		: G 
 * 7		: PAT
 * 6		: D 
 * 5		: A
 * 4 		: PCD
 * 3 		: PWT
 * 2		: U/S
 * 1		: R/W
 * 0		: P
 *
 * G: Global
 * 	Tells the processor not to invalidate the TLB entry corresponding to the page upon a MOV to CR3 instruction.
 * 	Bit 7 (PGE) in CR4 must be set to enable global pages.
 * PAT: Page Attribute Table
 * 	If PAT is supported, then PAT along with PCD and PWT shall indicate the memory caching type. Otherwise, it is reserved and must be set to 0.
 */