172 lines
4.0 KiB
C
172 lines
4.0 KiB
C
#ifdef __TESTING__
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#include <kernel/_kernel.h>
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#include <stdio.h>
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#endif
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#include <kernel/x86/io.h>
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#include <kernel/x86/pic.h>
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/** PIC I/O ports **/
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#define PIC1 0x20 /** Master PIC **/
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#define PIC2 0xA0 /** Slave PIC **/
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/** PIC helper defines **/
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#define PIC1_COMMAND (PIC1)
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#define PIC1_DATA (PIC1 + 1)
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#define PIC2_COMMAND (PIC2)
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#define PIC2_DATA (PIC2 + 1)
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/** PIC Commands **/
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#define ICW1_ICW4 0x01 /** Indicates ICW4 will be present **/
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#define ICW1_SINGLE 0x02 /** Single (cascade mode) **/
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#define ICW1_INTERVAL4 0x04 /** Call address interval 4 (8) **/
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#define ICW1_LEVEL 0x08 /** Level triggered (edge) mode **/
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#define ICW1_INIT 0x10 /** Initialization **/
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#define ICW4_8086 0x01 /** 8086/88 (MCS-80/85) mode **/
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#define ICW4_AUTO 0x02 /** Auto (normal) EOI **/
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#define ICW4_BUF_SLAVE 0x08 /** Buffered mode/slave **/
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#define ICW4_BUF_MASTER 0x0C /** Buffered mode/master **/
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#define ICW4_SFNM 0x10 /** Special fully nested (not) **/
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#define PIC_EOI 0x20 /** End-of-interrupt command code **/
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#define PIC_READ_IRR 0x0a /** OCW3 irq ready next CMD read **/
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#define PIC_READ_ISR 0x0b /** OCW3 irq service next CMD read **/
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void PIC_sendEOI(uint8_t irq)
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{
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if (irq >= 8) // if we're over the PIC1 limit
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outb(PIC2_COMMAND, PIC_EOI);
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outb(PIC1_COMMAND, PIC_EOI); // if the IRQ came from the slave, it must go to both PICs
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}
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void PIC_remap(int offset1, int offset2)
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{
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#ifdef __TESTING__
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kinfo("Remapping the PIC...");
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#endif
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// The io_wait calls are necessary for older machines, to give the PIC time to react
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//
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// After the init, the PIC requires 3 init words
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// ICW2 // its vector offset
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// ICW3 // how its wired to the master/slave
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// ICW4 // additional info about the environment
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outb(PIC1_COMMAND, ICW1_INIT | ICW1_ICW4); // starts the init sequence, in cascade mode
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io_wait();
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outb(PIC2_COMMAND, ICW1_INIT | ICW1_ICW4);
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io_wait();
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outb(PIC1_DATA, offset1); // ICW2 - the offset for master
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io_wait();
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outb(PIC2_DATA, offset2); // same as above for slave
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io_wait();
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outb(PIC1_DATA, 4); // ICW3 - Tells master theres a slave at IRQ2
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io_wait();
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outb(PIC2_DATA, 2); // ICW3 - Tells slave the cascade identity
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io_wait();
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outb(PIC1_DATA, ICW4_8086); // ICW4 - Use 8086 mode (not 8080 mode)
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io_wait();
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outb(PIC2_DATA, ICW4_8086);
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io_wait();
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// Unmask the PICs
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outb(PIC1_DATA, 0);
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outb(PIC2_DATA, 0);
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#ifdef __TESTING__
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kinfo("Remapped the PIC!");
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#endif
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}
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void pic_disable(void)
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{ // Mask the PIC interrupts to disable them
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outb(PIC1_DATA, 0xFF);
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outb(PIC2_DATA, 0xFF);
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#ifdef __TESTING__
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kinfo("Masked off the PIC");
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#endif
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}
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void IRQ_set_mask(uint8_t IRQline) // Masked IRQlines are ignored by the PIC, masked IRQ2 will fully ignore the slave
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{
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uint16_t port;
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uint8_t value;
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if (IRQline < 8) {
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port = PIC1_DATA;
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} else {
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port = PIC2_DATA;
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IRQline -= 8;
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}
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value = inb(port) | (1 << IRQline);
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outb(port, value);
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#ifdef __TESTING__
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kinfo("Masked IRQ line");
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printf("IRQ line: %d\n", IRQline);
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#endif
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}
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void IRQ_clear_mask(uint8_t IRQline)
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{
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uint16_t port;
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uint8_t value;
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if (IRQline < 8) {
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port = PIC1_DATA;
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} else {
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port = PIC2_DATA;
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IRQline -= 8;
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}
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value = inb(port) & ~(1 << IRQline);
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outb(port, value);
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#ifdef __TESTING__
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kinfo("Cleared mask from IRQ line");
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printf("IRQ line: %d\n", IRQline);
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#endif
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}
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static uint16_t __pic_get_irq_reg(int ocw3)
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{
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/** OCW3 to PIC CMD to get the register values
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* PIC2 is chained, and represents IRQs 8-1.
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* PIC1 is IRQs 0-7, with 2 being the chain **/
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outb(PIC1_COMMAND, ocw3);
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outb(PIC2_COMMAND, ocw3);
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return (inb(PIC2_COMMAND) << 8) | inb(PIC1_COMMAND);
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}
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uint16_t pic_get_irr(void)
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{
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return __pic_get_irq_reg(PIC_READ_IRR);
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}
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uint16_t pic_get_isr(void)
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{
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return __pic_get_irq_reg(PIC_READ_ISR);
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}
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#undef PIC1
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#undef PIC2
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#undef PIC1_COMMAND
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#undef PIC1_DATA
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#undef PIC2_COMMAND
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#undef PIC2_DATA
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#undef ICW1_ICW4
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#undef ICW1_SINGLE
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#undef ICW1_INTERVAL4
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#undef ICW1_LEVEL
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#undef ICW1_INIT
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#undef ICW4_8086
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#undef ICW4_AUTO
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#undef ICW4_BUF_SLAVE
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#undef ICW4_BUF_MASTER
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#undef ICW4_SFNM
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#undef PIC_EOI
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#undef PIC_READ_IRR
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#undef PIC_READ_ISR
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