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cleans up PIC

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This commit is contained in:
Nathan Singer
2025-06-13 16:09:47 -04:00
parent ed2c0a3568
commit 88921f024e
2 changed files with 46 additions and 33 deletions
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33
kernel/include/kernel/x86/pic.h
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@ -3,34 +3,6 @@
#ifndef ARCH_PIC_H
#define ARCH_PIC_H
/** PIC I/O ports **/
#define PIC1 0x20 /** Master PIC **/
#define PIC2 0xA0 /** Slave PIC **/
/** PIC helper defines **/
#define PIC1_COMMAND (PIC1)
#define PIC1_DATA (PIC1 + 1)
#define PIC2_COMMAND (PIC2)
#define PIC2_DATA (PIC2 + 1)
/** PIC Commands **/
#define ICW1_ICW4 0x01 /** Indicates ICW4 will be present **/
#define ICW1_SINGLE 0x02 /** Single (cascade mode) **/
#define ICW1_INTERVAL4 0x04 /** Call address interval 4 (8) **/
#define ICW1_LEVEL 0x08 /** Level triggered (edge) mode **/
#define ICW1_INIT 0x10 /** Initialization **/
#define ICW4_8086 0x01 /** 8086/88 (MCS-80/85) mode **/
#define ICW4_AUTO 0x02 /** Auto (normal) EOI **/
#define ICW4_BUF_SLAVE 0x08 /** Buffered mode/slave **/
#define ICW4_BUF_MASTER 0x0C /** Buffered mode/master **/
#define ICW4_SFNM 0x10 /** Special fully nested (not) **/
#define PIC_EOI 0x20 /** End-of-interrupt command code **/
#define PIC_READ_IRR 0x0a /** OCW3 irq ready next CMD read **/
#define PIC_READ_ISR 0x0b /** OCW3 irq service next CMD read **/
#define PIC_PIT 32
#define PIC_KEYB 33
#define PIC_CASCADE 34 // never raised
@ -63,11 +35,6 @@ void pic_disable(void);
void IRQ_set_mask(uint8_t IRQline);
void IRQ_clear_mask(uint8_t IRQline);
/** Returns the combined value of the cascaded PICs irq request register **/
uint16_t pic_get_irr(void);
/** Returns the combined value of the cascaded PICs in-service register **/
uint16_t pic_get_isr(void);
/**
* TODO: implement handling for Spurious IRQs
* https://wiki.osdev.org/8259_PIC#Spurious_IRQs